Development of compound semiconductor integrated technologies particularly in the solid state optics field have resulted in a need for high quality dielectrics and compound interfaces. This requirement is especially important for indium phosphide devices because indium phosphide and its alloy systems are well established as a base for discrete optical devices.
Recently the potential for high speed and high power indium phosphide devices has been demonstrated. The inherent material properties of indium phosphide, such as high electron peak and saturation velocity, low ionization rate, and high thermal conductivity, lead to higher frequency operation at higher powers than gallium arsenide devices. Furthermore, the surface potential of indium phosphide can be modulated over a substantial portion of the band gap, making the indium phosphide metal-insulated-semiconductor field effect transistor (MISFET) a viable device. Several research groups have now successfully fabricated indium phosphide MISFETs with high frequency and high power characteristics.
The requirement for high quality, low temperature dielectrics for applications in both group IV and group III-V semiconductor devices is particularly acute for indium phosphide devices because phosphorous begins to disassociate from the indium phosphide crystal at temperatures of 250.degree. to 300.degree. C. resulting in device deterioration. Further, high process temperatures can result in the interdiffusion of deposits and excessive penetration of metal alloys.
Unlike silicon, indium phosphide is not blessed with a good native dielectric. Although research is continuing on the controlled growth of native oxides for MIS structures, the techniques that have proven most successful thus far involve the deposition of foreign dielectrics such as Al.sub.2 O.sub.3, Si.sub.3 N.sub.4, and SiO.sub.2 on indium phosphide. These deposition processes however are constrained by the high vapor pressure of phosphorous, resulting in the above-mentioned disassociation. Deposition of SiO.sub.2, has been achieved by conventional plasma and photo enhanced reactions. However, the thermal nonequilibrium nature of these reactions make deposition of dense, uniform, stoichiometric SiO.sub.2 difficult to achieve. Thus deposition of these dielectrics by conventional means, has not so far allowed for the consistent production of high quality devices.
The most common approach for group III-V material is, therefore, to exploit various chemical vapor deposition (CVD) techniques based in silicon. These CVD techniques are used to deposit oxides and nitrides on a variety of substrates but the typical processes require temperatures of 400 to 1200 degrees C. While these temperatures pose few problems for purely silicon application they are unacceptable for most group III-V devices and some silicon processes.
A need therefore exists for a method of providing a high quality, low temperature dielectric for application in both group IV and III-V semiconductor devices. A further need exists for a low temperature dielectric deposition process that is capable of providing uniform and dense stoichiometric SiO.sub.2 layers on a variety of substrates without inducing substrate disassociation or interdiffusion.